The present invention generally pertains to systems for testing digital circuit units and is particularly directed to an improved digital circuit unit testing system utilizing signature analysis.
Signature analysis is a testing technique in which predetermined test patterns are applied to a unit under test, and the signals derived from various terminals and internal nodes of the unit in response to the test patterns are compressed and processed to provide a four-character signature. There are four bits for each character. The test patterns are calculated for maximum fault coverage by a computer. Signature analysis is fast and repeatable; and it provides extremely accurate results.
As digital circuit units continue to become more complex with the advent of microprocessors and very-large-scale integration (VLSI) devices, the number of predetermined test patterns that are needed for signature analysis testing becomes prohibitively larger in that tests of longer duration are required to maintain the level of accuracy associated with signature analysis testing. Such complexity also makes it more difficult to determine the location of faults in the unit under test. In addition, there is a considerable variation in the design speed of operation of the many different types of digital circuit units.